46 int *left,
int *left_top)
52 "movq (%1, %0), %%mm0 \n\t"
53 "psllq $8, %%mm0 \n\t"
55 "movq (%1, %0), %%mm1 \n\t"
56 "movq -1(%2, %0), %%mm2 \n\t"
57 "movq (%2, %0), %%mm3 \n\t"
58 "movq %%mm2, %%mm4 \n\t"
59 "psubb %%mm0, %%mm2 \n\t"
60 "paddb %%mm1, %%mm2 \n\t"
61 "movq %%mm4, %%mm5 \n\t"
62 "pmaxub %%mm1, %%mm4 \n\t"
63 "pminub %%mm5, %%mm1 \n\t"
64 "pminub %%mm2, %%mm4 \n\t"
65 "pmaxub %%mm1, %%mm4 \n\t"
66 "psubb %%mm4, %%mm3 \n\t"
67 "movq %%mm3, (%3, %0) \n\t"
69 "movq -1(%1, %0), %%mm0 \n\t"
80 *left_top =
src1[
w - 1];
96 c->sub_median_pred = sub_median_pred_mmxext;
__asm__(".macro parse_r var r\n\t" "\\var = -1\n\t" _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) ".iflt \\var\n\t" ".error \"Unable to parse register name \\r\"\n\t" ".endif\n\t" ".endm")
Macro definitions for various function/variable attributes.
static atomic_int cpu_flags
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
void ff_diff_bytes_avx2(uint8_t *dst, const uint8_t *src1, const uint8_t *src2, intptr_t w)
void ff_sub_left_predict_avx(uint8_t *dst, uint8_t *src, ptrdiff_t stride, ptrdiff_t width, int height)
av_cold void ff_llvidencdsp_init_x86(LLVidEncDSPContext *c)
void ff_diff_bytes_sse2(uint8_t *dst, const uint8_t *src1, const uint8_t *src2, intptr_t w)
void ff_diff_bytes_mmx(uint8_t *dst, const uint8_t *src1, const uint8_t *src2, intptr_t w)
#define EXTERNAL_AVX(flags)
#define EXTERNAL_AVX2_FAST(flags)
#define INLINE_MMXEXT(flags)
#define EXTERNAL_MMX(flags)
#define EXTERNAL_SSE2(flags)